# Spi_Master Example Code

## Project Name: Spi_Master

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## Function description

This project is designed to demonstrate the Spi master module config and usage:
- **Spi_Master**: 
  - As master,the SPI initiates and controlsall data transactions.

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## HW requirement
+ **EVB**: YTM32B1M-EVB-Q144
+ **Debugger**: J-LINK v9.2 or later with YUNTU YTM32B1ME0 patch(support package) installed.

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## SW requirement

+ **Config & Code Generation Tool**
  + **SDK**:       Yuntu Config Tool(YCT) v2.6.3 or later version
+ **Compiler Toolchain**
  + **GCC***     : GNU GCC v10.3 or later version
  + **Keil/MDK***: ARM Keil/MDK v5.36 or later version
  + **IAR***     : IAR v8.4 or later version
  + **VS Code**  : Microsoft Visual Studio Code IDE v1.76 or later version(C/C++ support, GNU toolchain, CMake v3.25, ninja, Cortex-Debug extensions installation required)
+ **Debugger driver**
    + **J-LINK***              : SEGGER JLINK v6.96 or later version, YUNTU YTM32B1ME0 patch(support package) installation required.
    + **Ozone Debugger tool**  : SEGGER Ozone v3.28 or later version.

    ***Note***: * **YTM32B1ME0** patch install required which can be obtained via **YCT** or contact ***YUNTU sales/FAE team***.

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## Setup

+ ***Step1***: Open the project.yct with the YCT tool, config the toolchain per your required(by default, the VS code + GCC are used)
+ ***Step2***: Generate the codes, you can change the configurations if needed(to adapt to your own HW design), if so, please ensure all the modifications are OK with no any errors exist before generating the code.
+ ***Step3***: Open the generated project with VS code/IAR/Keil IDE per your selected.
+ ***Step4***: Compile the project, power on the EVB and download it to the EVB via the available debugger, such as a J-LINK debugger probe.
+ ***Step5***: At last, enjoy the demo example.
  
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1. Config alt value of PTA_9 Pin with LINFlexD2_TX as TX pin and PTA_8 with LINFlexD2_RX as RX pin.
2. Enable and config LINFlexD2_CLK.
3. Enable and config Linflexd Uart and Utility Print module.
4. Spi master transfer data.
  
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