/* USER CODE BEGIN Header */
/* you can remove the copyright */
/*
 * Copyright 2020-2026 Yuntu Microelectronics Co., Ltd.
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 * 
 * @file main.c
 * @brief 
 * 
 */

/* USER CODE END Header */
#include "sdk_project_config.h"
/* Includes ------------------------------------------------------------------*/
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */

/* Private typedef -----------------------------------------------------------*/
/* USER CODE BEGIN PTD */
#define ADC_INT_ENABLE  false//true
#define ADC_INST    (0) /* ADC instance */
#define SEQ_LEN     (3) /* channel number */
/* USER CODE END PTD */

/* Private define ------------------------------------------------------------*/
/* USER CODE BEGIN PD */
volatile uint16_t g_adc_result[8];
dma_loop_transfer_config_t adcLoopTransferConfig = { .triggerLoopIterationCount = 3, /*! Total ADC trigger count */
                                                     .dstOffsetEnable = true,
                                                     .triggerLoopOffset = -(SEQ_LEN * 2) 
                                                     };

const dma_transfer_config_t adcTransferConfig = { .srcAddr = (uint32_t)&ADC0->FIFO,
                                                  .destAddr = (uint32_t)&g_adc_result[0U],
                                                  .destOffset = 0x02U,
                                                  .srcOffset = 0x00U,
                                                  .srcTransferSize = DMA_TRANSFER_SIZE_2B,
                                                  .destTransferSize = DMA_TRANSFER_SIZE_2B,
                                                  .srcModulo = DMA_MODULO_OFF,
                                                  .destModulo = DMA_MODULO_OFF,
                                                  .transferLoopByteCount = (SEQ_LEN * 2),
                                                  .loopTransferConfig = &adcLoopTransferConfig,
                                                  .destLastAddrAdjust = -(SEQ_LEN * 2),
                                                  .interruptEnable = false };
/* USER CODE END PV */
/* USER CODE END PD */

/* Private macro -------------------------------------------------------------*/
/* USER CODE BEGIN PM */
/* The period count is 3750, PWM=16Khz=62.5us，PTU=60Mhz, Sum cnt = 62.5us*60 cnt/us =3750 cnt*/
const uint32_t PTU_PERIOD_COUNT   = 3750;  
const uint32_t PTU_BASE_COUNT     = 0;
/* The offset count is 200, delay 200 cnt/60 cnt/us= 3.33us to trigger the first AD channel */
const uint32_t PTU_OFFSET_COUNT0  = 200;
/* The offset count is 1000, delay 1000 cnt/60 cnt/us= 16.67us to trigger the second AD channel */
const uint32_t PTU_OFFSET_COUNT1  = 1000;
/* The offset count is 2500, delay 2500 cnt/60 cnt/us= 41.67us to trigger the third AD channel */
const uint32_t PTU_OFFSET_COUNT2  = 2500;

/* USER CODE END PM */

/* Private variables ---------------------------------------------------------*/
/* USER CODE BEGIN PV */
const ptu_adc_pretrigger_config_t ptu_HardwareTrigger_pdly1_AdcTrigInitConfig0 = {
  .adcPreTriggerIdx = 0U,
  .preTriggerEnable = true,
  .preTriggerOutputEnable = true,
};

const ptu_adc_pretrigger_config_t ptu_HardwareTrigger_pdly1_AdcTrigInitConfig1 = {
  .adcPreTriggerIdx = 1U,
  .preTriggerEnable = true,
  .preTriggerOutputEnable = true,
};

const ptu_adc_pretrigger_config_t ptu_HardwareTrigger_pdly1_AdcTrigInitConfig2 = {
  .adcPreTriggerIdx = 2U,
  .preTriggerEnable = true,
  .preTriggerOutputEnable = true,
};


/* USER CODE END PV */

/* Private function declare --------------------------------------------------*/
/* USER CODE BEGIN PFDC */
uint8_t i = 0;
/* USER CODE END PFDC */
static void Board_Init(void);

/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
#if ADC_INT_ENABLE
void ADC0_IRQHandler(void)
{
  if(ADC_DRV_GetEndOfSequenceFlag(ADC_INST))
  {
    ADC_DRV_ClearEoseqFlagCmd(ADC_INST);
  }
  else
  {
    ADC_DRV_ClearEocFlagCmd(ADC_INST);
    if(i < 2)
    {
      g_adc_result[i]=ADC_DRV_ReadFIFO(ADC_INST);
      i++;    
    }
    else
    {
      
      g_adc_result[i]=ADC_DRV_ReadFIFO(ADC_INST);
      i = 0;
    }
  }
}
#endif
/* USER CODE END 0 */


/**
 * @brief  The application entry point.
 * @retval int
 */
int main(void)
{
    /* USER CODE BEGIN 1 */
    /* USER CODE END 1 */ 
    Board_Init();
    /* USER CODE BEGIN 2 */  
    #if  ADC_INT_ENABLE
    ADC_DRV_ConfigConverter(0,&adc_config_int);
    INT_SYS_EnableIRQ(ADC0_IRQn);
    #else
    ADC_DRV_ConfigConverter(0,&adc_config_dma);
    DMA_DRV_ConfigLoopTransfer(0U, &adcTransferConfig);
    DMA_DRV_StartChannel(0U);
    #endif

    PTU_DRV_Enable(0);
    PTU_DRV_ConfigAdcPreTrigger(0, &ptu_HardwareTrigger_pdly1_AdcTrigInitConfig0);
    PTU_DRV_ConfigAdcPreTrigger(0, &ptu_HardwareTrigger_pdly1_AdcTrigInitConfig1);
    PTU_DRV_ConfigAdcPreTrigger(0, &ptu_HardwareTrigger_pdly1_AdcTrigInitConfig2);
    PTU_DRV_SetTimerModulusValue(0, (uint32_t) PTU_PERIOD_COUNT);
    PTU_DRV_SetAdcPreTriggerDelayValue(0, 0UL,(uint32_t) PTU_BASE_COUNT + PTU_OFFSET_COUNT0);
    PTU_DRV_SetAdcPreTriggerDelayValue(0, 1UL,(uint32_t) PTU_BASE_COUNT + PTU_OFFSET_COUNT1);
    PTU_DRV_SetAdcPreTriggerDelayValue(0, 2UL,(uint32_t) PTU_BASE_COUNT + PTU_OFFSET_COUNT2);
    PTU_DRV_LoadValuesCmd(0);   

    ADC_DRV_Start(ADC_INST);
    /* Enable the eTMR */
    eTMR_DRV_Enable(0);
    /* USER CODE END 2 */

    /* Infinite loop */
    /* USER CODE BEGIN WHILE */
    while (1)
    {
        /* USER CODE END WHILE */
        /* USER CODE BEGIN 3 */
    }
    /* USER CODE END 3 */
}

static void Board_Init(void)
{
    CLOCK_SYS_Init(g_clockManConfigsArr,CLOCK_MANAGER_CONFIG_CNT,g_clockManCallbacksArr,CLOCK_MANAGER_CALLBACK_CNT);
    if(STATUS_SUCCESS != CLOCK_SYS_UpdateConfiguration(CLOCK_MANAGER_ACTIVE_INDEX,CLOCK_MANAGER_POLICY_AGREEMENT))
    {
        /* USER CODE BEGIN ERROR_HANDLER 1 */
        SystemSoftwareReset();
        /* USER CODE END ERROR_HANDLER 1 */
    }
    PINS_DRV_Init(NUM_OF_CONFIGURED_PINS0,g_pin_mux_InitConfigArr0);
    UTILITY_PRINT_Init();
    TMU_DRV_Init(0,&tmu_config0);
    PTU_DRV_Init(0,&ptu_config0);
    eTMR_DRV_Init(0,&ETMR_CM_Config0,&ETMR_CM_Config0_State);
    eTMR_DRV_InitPwm(0,&ETMR_PWM_Config0);
    DMA_DRV_Init(&dmaState,&dmaController_InitConfig,dmaChnState,dmaChnConfigArray,NUM_OF_CONFIGURED_DMA_CHANNEL);
}

/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
