for (uint16 MpwmIndex = 0U; MpwmIndex < Icu_gConfigPtr->IcuMpwmConfigPtr->IcuMpwmInstanceCount; MpwmIndex++)
    {
        IcuMpwmConfigPtr = &Icu_gConfigPtr->IcuMpwmConfigPtr[MpwmIndex];
        MpwmInstanceId = IcuMpwmConfigPtr->IcuMpwmInstance;
        MpwmBaseAddress = (uint32)Icu_Mpwm_Common_gBaseAddress32[MpwmInstanceId];
        for (uint16 MpwmChannelIndex = 0U; MpwmChannelIndex < IcuMpwmConfigPtr->IcuMpwmChannelCount; MpwmChannelIndex++)
        {
            MpwmInstanceId = IcuMpwmConfigPtr->IcuMpwmInstance;
            MpwmChannelId = IcuMpwmConfigPtr->IcuMpwmChannelPtr[MpwmChannelIndex].IcuMpwmChannel;
            Mpwm_ChannelInfo[MpwmInstanceId][MpwmChannelId].PeriodTime = IcuMpwmConfigPtr->IcuMpwmChannelPtr[MpwmChannelIndex].IcuMpwmPeriod;
            /* Set default edge detection notification */
            MpwmBaseAddress = (uint32)Icu_Mpwm_Common_gBaseAddress32[MpwmInstanceId];
            ICU_MPWM_REG_ADDR32_WRITE(MpwmBaseAddress + MPWM_CH_PERIOD_OFFSET32(MpwmChannelId), Mpwm_ChannelInfo[MpwmInstanceId][MpwmChannelId].PeriodTime);
            ICU_MPWM_REG_ADDR32_SET_BITS(MpwmBaseAddress + MPWM_CH_CFG_OFFSET32(MpwmChannelId), MPWM_CH_CFG_CLKPRS(IcuMpwmConfigPtr->IcuMpwmChannelPtr[MpwmChannelIndex].IcuMpwmPrescaler));
            ICU_MPWM_REG_ADDR32_SET_BITS(MpwmBaseAddress + MPWM_CH_CFG_OFFSET32(MpwmChannelId), MPWM_CH_CFG_ONESHOT(IcuMpwmConfigPtr->IcuMpwmChannelPtr[MpwmChannelIndex].IcuMpwmCountMode));
            ICU_MPWM_REG_ADDR32_SET_BITS(MpwmBaseAddress + MPWM_CH_CFG_OFFSET32(MpwmChannelId), MPWM_CH_CFG_DBGDIS(IcuMpwmConfigPtr->IcuMpwmChannelPtr[MpwmChannelIndex].IcuMpwmDebug));
            ICU_MPWM_REG_ADDR32_SET_BITS(MpwmBaseAddress + MPWM_INTE1_OFFSET32, 0x01U << MpwmChannelId); /* Enable all Channel event occurs interrupts */
            ICU_MPWM_REG_ADDR32_SET_BITS(MpwmBaseAddress + MPWM_INTE0_OFFSET32, 0x01U << MpwmChannelId); /* Enable all Timer Overflow interrupts */
            ICU_MPWM_REG_ADDR32_SET_BITS(MpwmBaseAddress + MPWM_CH_CFG_OFFSET32(MpwmChannelId), MPWM_CH_CFG_CHMODE(MPWM_INPUT_CAPTURE));
        }
        ICU_MPWM_REG_ADDR32_WRITE(MpwmBaseAddress + MPWM_STS1_OFFSET32, 0xffffffffU); /* Clear all Channel event occurs flags */
    }