/**
*   @file    pSIP_Pcu.h
*   @version
*
*   @brief   AUTOSAR Pcu register map
*   @details Register map for PCU
*
*   @addtogroup PCU_MODULE
*   @{
*/
/*==================================================================================================
*   Project              : YTMicro AUTOSAR 4.4.0 MCAL
*   Platform             : ARM
*   Peripheral           : Pcu
*   Dependencies         : none
*
*   Autosar Version      : V4.4.0
*   Autosar Revision     : ASR_REL_4_4_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : V0.8.0
*
*   (c) Copyright 2020-2026 Jiangsu Yuntu Microelectronics CO,. LTD.
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/

#ifndef PSIP_PCU_H
#define PSIP_PCU_H

/*=================================================================================================
*                                        INCLUDE FILES
=================================================================================================*/

#include "Std_Types.h"

/*==================================================================================================
*                              PCU REGISTER MAP
==================================================================================================*/

/**
 * @addtogroup PCU_Peripheral_Access_Layer PCU Peripheral Access Layer
 * @{
 */


/** PCU - Size of Registers Arrays */

/* PCU Register Layout Typedef */
typedef struct
{
    uint32 SSTS;                               /**< Sticky Status Register, offset: 0x0000 */
    uint32 STS;                                /**< Status Register, offset: 0x0004 */
    uint32 INTE;                               /**< Interrupt Register, offset: 0x0008 */
    uint32 CTRL0;                              /**< Control Register 0, offset: 0x000C */
    uint32 CTRL1;                              /**< Control Register 1, offset: 0x0010 */
    uint32 TRIM0;                              /**< Trim Register 0, offset: 0x0014 */
    uint32 RESERVED6;                          /**< RESERVED6, offset: 0x0018 */
    uint32 RESERVED7;                          /**< RESERVED7, offset: 0x001C */

} PCU_Type, *PCU_MemMapPtr;

/** Number of instances of the PCU module. */
#define PCU_INSTANCE_COUNT                        (1u)

/* PCU base address */
#define PCU_BASE_ADDR32                                   (0x401F8000U)
#define PCU                                               ((volatile PCU_Type *)(PCU_BASE_ADDR32))

/** Array initializer of PCU peripheral base addresses */
#define PCU_BASE_ADDRS                                     { PCU_BASE_ADDR32 }
/** Array initializer of PCU peripheral base pointers */
#define PCU_BASE_PTRS                                      { PCU }

#define PCU_SSTS_OFFSET32                                  (0x0000U)                    /**< Offset for Sticky Status Register */
#define PCU_STS_OFFSET32                                   (0x0004U)                    /**< Offset for Status Register */
#define PCU_INTE_OFFSET32                                  (0x0008U)                    /**< Offset for Interrupt Register */
#define PCU_CTRL0_OFFSET32                                 (0x000CU)                    /**< Offset for Control Register 0 */
#define PCU_CTRL1_OFFSET32                                 (0x0010U)                    /**< Offset for Control Register 1 */
#define PCU_TRIM0_OFFSET32                                 (0x0014U)                    /**< Offset for Trim Register 0 */


/**
 * @addtogroup PCU Register Mask
 * @{
 */
/* PCU_SSTS Register */
#define PCU_SSTS_PORF_MASK                                 (0x80000000U)
#define PCU_SSTS_PORF_SHIFT                                (31U)
#define PCU_SSTS_PORF(x)                                   (((uint32)(((uint32)(x)) << PCU_SSTS_PORF_SHIFT)) & PCU_SSTS_PORF_MASK)
#define PCU_SSTS_LVD12F_MASK                               (0x10000U)
#define PCU_SSTS_LVD12F_SHIFT                              (16U)
#define PCU_SSTS_LVD12F(x)                                 (((uint32)(((uint32)(x)) << PCU_SSTS_LVD12F_SHIFT)) & PCU_SSTS_LVD12F_MASK)
#define PCU_SSTS_HVD50F_MASK                               (0x10U)
#define PCU_SSTS_HVD50F_SHIFT                              (4U)
#define PCU_SSTS_HVD50F(x)                                 (((uint32)(((uint32)(x)) << PCU_SSTS_HVD50F_SHIFT)) & PCU_SSTS_HVD50F_MASK)
#define PCU_SSTS_LVD50F_MASK                               (0x1U)
#define PCU_SSTS_LVD50F_SHIFT                              (0U)
#define PCU_SSTS_LVD50F(x)                                 (((uint32)(((uint32)(x)) << PCU_SSTS_LVD50F_SHIFT)) & PCU_SSTS_LVD50F_MASK)
/* PCU_STS Register */
#define PCU_STS_HPRDY_MASK                                 (0x1000000U)
#define PCU_STS_HPRDY_SHIFT                                (24U)
#define PCU_STS_HPRDY(x)                                   (((uint32)(((uint32)(x)) << PCU_STS_HPRDY_SHIFT)) & PCU_STS_HPRDY_MASK)
#define PCU_STS_LVD12S_MASK                                (0x10000U)
#define PCU_STS_LVD12S_SHIFT                               (16U)
#define PCU_STS_LVD12S(x)                                  (((uint32)(((uint32)(x)) << PCU_STS_LVD12S_SHIFT)) & PCU_STS_LVD12S_MASK)
#define PCU_STS_HVD50S_MASK                                (0x10U)
#define PCU_STS_HVD50S_SHIFT                               (4U)
#define PCU_STS_HVD50S(x)                                  (((uint32)(((uint32)(x)) << PCU_STS_HVD50S_SHIFT)) & PCU_STS_HVD50S_MASK)
#define PCU_STS_LVD50S_MASK                                (0x1U)
#define PCU_STS_LVD50S_SHIFT                               (0U)
#define PCU_STS_LVD50S(x)                                  (((uint32)(((uint32)(x)) << PCU_STS_LVD50S_SHIFT)) & PCU_STS_LVD50S_MASK)
/* PCU_INTE Register */
#define PCU_INTE_HVDIE_MASK                                (0x8000U)
#define PCU_INTE_HVDIE_SHIFT                               (15U)
#define PCU_INTE_HVDIE(x)                                  (((uint32)(((uint32)(x)) << PCU_INTE_HVDIE_SHIFT)) & PCU_INTE_HVDIE_MASK)
#define PCU_INTE_LVDIE_MASK                                (0x4000U)
#define PCU_INTE_LVDIE_SHIFT                               (14U)
#define PCU_INTE_LVDIE(x)                                  (((uint32)(((uint32)(x)) << PCU_INTE_LVDIE_SHIFT)) & PCU_INTE_LVDIE_MASK)
/* PCU_CTRL0 Register */
#define PCU_CTRL0_SET1V_MASK                               (0x80000000U)
#define PCU_CTRL0_SET1V_SHIFT                              (31U)
#define PCU_CTRL0_SET1V(x)                                 (((uint32)(((uint32)(x)) << PCU_CTRL0_SET1V_SHIFT)) & PCU_CTRL0_SET1V_MASK)
#define PCU_CTRL0_DPD_WK2_EN_MASK                          (0x40000000U)
#define PCU_CTRL0_DPD_WK2_EN_SHIFT                         (30U)
#define PCU_CTRL0_DPD_WK2_EN(x)                            (((uint32)(((uint32)(x)) << PCU_CTRL0_DPD_WK2_EN_SHIFT)) & PCU_CTRL0_DPD_WK2_EN_MASK)
#define PCU_CTRL0_DPD_WK1_EN_MASK                          (0x20000000U)
#define PCU_CTRL0_DPD_WK1_EN_SHIFT                         (29U)
#define PCU_CTRL0_DPD_WK1_EN(x)                            (((uint32)(((uint32)(x)) << PCU_CTRL0_DPD_WK1_EN_SHIFT)) & PCU_CTRL0_DPD_WK1_EN_MASK)
#define PCU_CTRL0_DPD_WK0_EN_MASK                          (0x10000000U)
#define PCU_CTRL0_DPD_WK0_EN_SHIFT                         (28U)
#define PCU_CTRL0_DPD_WK0_EN(x)                            (((uint32)(((uint32)(x)) << PCU_CTRL0_DPD_WK0_EN_SHIFT)) & PCU_CTRL0_DPD_WK0_EN_MASK)
#define PCU_CTRL0_HVD50_LPMD_MASK                          (0x4000000U)
#define PCU_CTRL0_HVD50_LPMD_SHIFT                         (26U)
#define PCU_CTRL0_HVD50_LPMD(x)                            (((uint32)(((uint32)(x)) << PCU_CTRL0_HVD50_LPMD_SHIFT)) & PCU_CTRL0_HVD50_LPMD_MASK)
#define PCU_CTRL0_LVD50_LPMD_MASK                          (0x1000000U)
#define PCU_CTRL0_LVD50_LPMD_SHIFT                         (24U)
#define PCU_CTRL0_LVD50_LPMD(x)                            (((uint32)(((uint32)(x)) << PCU_CTRL0_LVD50_LPMD_SHIFT)) & PCU_CTRL0_LVD50_LPMD_MASK)
#define PCU_CTRL0_ESCFG_MASK                               (0xF00000U)
#define PCU_CTRL0_ESCFG_SHIFT                              (20U)
#define PCU_CTRL0_ESCFG(x)                                 (((uint32)(((uint32)(x)) << PCU_CTRL0_ESCFG_SHIFT)) & PCU_CTRL0_ESCFG_MASK)
#define PCU_CTRL0_FLTCFG_MASK                              (0xC0000U)
#define PCU_CTRL0_FLTCFG_SHIFT                             (18U)
#define PCU_CTRL0_FLTCFG(x)                                (((uint32)(((uint32)(x)) << PCU_CTRL0_FLTCFG_SHIFT)) & PCU_CTRL0_FLTCFG_MASK)
#define PCU_CTRL0_HVD50_FLTEN_MASK                         (0x20000U)
#define PCU_CTRL0_HVD50_FLTEN_SHIFT                        (17U)
#define PCU_CTRL0_HVD50_FLTEN(x)                           (((uint32)(((uint32)(x)) << PCU_CTRL0_HVD50_FLTEN_SHIFT)) & PCU_CTRL0_HVD50_FLTEN_MASK)
#define PCU_CTRL0_LVD50_FLTEN_MASK                         (0x10000U)
#define PCU_CTRL0_LVD50_FLTEN_SHIFT                        (16U)
#define PCU_CTRL0_LVD50_FLTEN(x)                           (((uint32)(((uint32)(x)) << PCU_CTRL0_LVD50_FLTEN_SHIFT)) & PCU_CTRL0_LVD50_FLTEN_MASK)
#define PCU_CTRL0_HVDRE_MASK                               (0x8000U)
#define PCU_CTRL0_HVDRE_SHIFT                              (15U)
#define PCU_CTRL0_HVDRE(x)                                 (((uint32)(((uint32)(x)) << PCU_CTRL0_HVDRE_SHIFT)) & PCU_CTRL0_HVDRE_MASK)
#define PCU_CTRL0_LVDRE_MASK                               (0x4000U)
#define PCU_CTRL0_LVDRE_SHIFT                              (14U)
#define PCU_CTRL0_LVDRE(x)                                 (((uint32)(((uint32)(x)) << PCU_CTRL0_LVDRE_SHIFT)) & PCU_CTRL0_LVDRE_MASK)
#define PCU_CTRL0_HVD50EN_MASK                             (0x400U)
#define PCU_CTRL0_HVD50EN_SHIFT                            (10U)
#define PCU_CTRL0_HVD50EN(x)                               (((uint32)(((uint32)(x)) << PCU_CTRL0_HVD50EN_SHIFT)) & PCU_CTRL0_HVD50EN_MASK)
#define PCU_CTRL0_LVD12EN_MASK                             (0x200U)
#define PCU_CTRL0_LVD12EN_SHIFT                            (9U)
#define PCU_CTRL0_LVD12EN(x)                               (((uint32)(((uint32)(x)) << PCU_CTRL0_LVD12EN_SHIFT)) & PCU_CTRL0_LVD12EN_MASK)
#define PCU_CTRL0_LVD50EN_MASK                             (0x100U)
#define PCU_CTRL0_LVD50EN_SHIFT                            (8U)
#define PCU_CTRL0_LVD50EN(x)                               (((uint32)(((uint32)(x)) << PCU_CTRL0_LVD50EN_SHIFT)) & PCU_CTRL0_LVD50EN_MASK)
#define PCU_CTRL0_PKE_MASK                                 (0x80U)
#define PCU_CTRL0_PKE_SHIFT                                (7U)
#define PCU_CTRL0_PKE(x)                                   (((uint32)(((uint32)(x)) << PCU_CTRL0_PKE_SHIFT)) & PCU_CTRL0_PKE_MASK)
#define PCU_CTRL0_HPRDY_CFG_MASK                           (0x30U)
#define PCU_CTRL0_HPRDY_CFG_SHIFT                          (4U)
#define PCU_CTRL0_HPRDY_CFG(x)                             (((uint32)(((uint32)(x)) << PCU_CTRL0_HPRDY_CFG_SHIFT)) & PCU_CTRL0_HPRDY_CFG_MASK)
#define PCU_CTRL0_PWR_MODE_MASK                            (0x7U)
#define PCU_CTRL0_PWR_MODE_SHIFT                           (0U)
#define PCU_CTRL0_PWR_MODE(x)                              (((uint32)(((uint32)(x)) << PCU_CTRL0_PWR_MODE_SHIFT)) & PCU_CTRL0_PWR_MODE_MASK)
/* PCU_CTRL1 Register */
#define PCU_CTRL1_DS_RAM_RETEN_MASK                        (0x1000000U)
#define PCU_CTRL1_DS_RAM_RETEN_SHIFT                       (24U)
#define PCU_CTRL1_DS_RAM_RETEN(x)                          (((uint32)(((uint32)(x)) << PCU_CTRL1_DS_RAM_RETEN_SHIFT)) & PCU_CTRL1_DS_RAM_RETEN_MASK)
#define PCU_CTRL1_PD_OCRAMU3U_PSDEN_MASK                     (0x20000U)
#define PCU_CTRL1_PD_OCRAMU3U_PSDEN_SHIFT                    (17U)
#define PCU_CTRL1_PD_OCRAMU3U_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_PD_OCRAMU3U_PSDEN_SHIFT)) & PCU_CTRL1_PD_OCRAMU3U_PSDEN_MASK)
#define PCU_CTRL1_PD_OCRAMU3L_PSDEN_MASK                     (0x10000U)
#define PCU_CTRL1_PD_OCRAMU3L_PSDEN_SHIFT                    (16U)
#define PCU_CTRL1_PD_OCRAMU3L_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_PD_OCRAMU3L_PSDEN_SHIFT)) & PCU_CTRL1_PD_OCRAMU3L_PSDEN_MASK)
#define PCU_CTRL1_STDBY_DMA_PSDEN_MASK                     (0x1000U)
#define PCU_CTRL1_STDBY_DMA_PSDEN_SHIFT                    (12U)
#define PCU_CTRL1_STDBY_DMA_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_DMA_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_DMA_PSDEN_MASK)
#define PCU_CTRL1_STDBY_CAN_PSDEN_MASK                     (0x800U)
#define PCU_CTRL1_STDBY_CAN_PSDEN_SHIFT                    (11U)
#define PCU_CTRL1_STDBY_CAN_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_CAN_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_CAN_PSDEN_MASK)
#define PCU_CTRL1_STDBY_CACHE_PSDEN_MASK                     (0x400U)
#define PCU_CTRL1_STDBY_CACHE_PSDEN_SHIFT                    (10U)
#define PCU_CTRL1_STDBY_CACHE_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_CACHE_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_CACHE_PSDEN_MASK)
#define PCU_CTRL1_STDBY_ROM_PSDEN_MASK                     (0x200U)
#define PCU_CTRL1_STDBY_ROM_PSDEN_SHIFT                    (9U)
#define PCU_CTRL1_STDBY_ROM_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_ROM_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_ROM_PSDEN_MASK)
#define PCU_CTRL1_STDBY_OCRAMU3U_PSDEN_MASK                     (0x100U)
#define PCU_CTRL1_STDBY_OCRAMU3U_PSDEN_SHIFT                    (8U)
#define PCU_CTRL1_STDBY_OCRAMU3U_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_OCRAMU3U_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_OCRAMU3U_PSDEN_MASK)
#define PCU_CTRL1_STDBY_OCRAMU3L_PSDEN_MASK                     (0x80U)
#define PCU_CTRL1_STDBY_OCRAMU3L_PSDEN_SHIFT                    (7U)
#define PCU_CTRL1_STDBY_OCRAMU3L_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_OCRAMU3L_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_OCRAMU3L_PSDEN_MASK)
#define PCU_CTRL1_STDBY_OCRAMU2_PSDEN_MASK                     (0x40U)
#define PCU_CTRL1_STDBY_OCRAMU2_PSDEN_SHIFT                    (6U)
#define PCU_CTRL1_STDBY_OCRAMU2_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_OCRAMU2_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_OCRAMU2_PSDEN_MASK)
#define PCU_CTRL1_STDBY_OCRAMU1_PSDEN_MASK                     (0x20U)
#define PCU_CTRL1_STDBY_OCRAMU1_PSDEN_SHIFT                    (5U)
#define PCU_CTRL1_STDBY_OCRAMU1_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_OCRAMU1_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_OCRAMU1_PSDEN_MASK)
#define PCU_CTRL1_STDBY_OCRAMU0_PSDEN_MASK                     (0x10U)
#define PCU_CTRL1_STDBY_OCRAMU0_PSDEN_SHIFT                    (4U)
#define PCU_CTRL1_STDBY_OCRAMU0_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_OCRAMU0_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_OCRAMU0_PSDEN_MASK)
#define PCU_CTRL1_STDBY_OCRAML3_PSDEN_MASK                     (0x8U)
#define PCU_CTRL1_STDBY_OCRAML3_PSDEN_SHIFT                    (3U)
#define PCU_CTRL1_STDBY_OCRAML3_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_OCRAML3_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_OCRAML3_PSDEN_MASK)
#define PCU_CTRL1_STDBY_OCRAML2_PSDEN_MASK                     (0x4U)
#define PCU_CTRL1_STDBY_OCRAML2_PSDEN_SHIFT                    (2U)
#define PCU_CTRL1_STDBY_OCRAML2_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_OCRAML2_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_OCRAML2_PSDEN_MASK)
#define PCU_CTRL1_STDBY_OCRAML1_PSDEN_MASK                     (0x2U)
#define PCU_CTRL1_STDBY_OCRAML1_PSDEN_SHIFT                    (1U)
#define PCU_CTRL1_STDBY_OCRAML1_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_OCRAML1_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_OCRAML1_PSDEN_MASK)
#define PCU_CTRL1_STDBY_OCRAML0_PSDEN_MASK                     (0x1U)
#define PCU_CTRL1_STDBY_OCRAML0_PSDEN_SHIFT                    (0U)
#define PCU_CTRL1_STDBY_OCRAML0_PSDEN(x)                       (((uint32)(((uint32)(x)) << PCU_CTRL1_STDBY_OCRAML0_PSDEN_SHIFT)) & PCU_CTRL1_STDBY_OCRAML0_PSDEN_MASK)
/* PCU_TRIM0 Register */
#define PCU_TRIM0_LVD12HYS_MASK                            (0xC00000U)
#define PCU_TRIM0_LVD12HYS_SHIFT                           (22U)
#define PCU_TRIM0_LVD12HYS(x)                              (((uint32)(((uint32)(x)) << PCU_TRIM0_LVD12HYS_SHIFT)) & PCU_TRIM0_LVD12HYS_MASK)
#define PCU_TRIM0_LVD12_TRIM_MASK                          (0x70000U)
#define PCU_TRIM0_LVD12_TRIM_SHIFT                         (16U)
#define PCU_TRIM0_LVD12_TRIM(x)                            (((uint32)(((uint32)(x)) << PCU_TRIM0_LVD12_TRIM_SHIFT)) & PCU_TRIM0_LVD12_TRIM_MASK)
#define PCU_TRIM0_HVD50_TRIM_MASK                          (0x300U)
#define PCU_TRIM0_HVD50_TRIM_SHIFT                         (8U)
#define PCU_TRIM0_HVD50_TRIM(x)                            (((uint32)(((uint32)(x)) << PCU_TRIM0_HVD50_TRIM_SHIFT)) & PCU_TRIM0_HVD50_TRIM_MASK)
#define PCU_TRIM0_HLVD50HYS_MASK                           (0xC0U)
#define PCU_TRIM0_HLVD50HYS_SHIFT                          (6U)
#define PCU_TRIM0_HLVD50HYS(x)                             (((uint32)(((uint32)(x)) << PCU_TRIM0_HLVD50HYS_SHIFT)) & PCU_TRIM0_HLVD50HYS_MASK)
#define PCU_TRIM0_LVD50_TRIM_MASK                          (0x7U)
#define PCU_TRIM0_LVD50_TRIM_SHIFT                         (0U)
#define PCU_TRIM0_LVD50_TRIM(x)                            (((uint32)(((uint32)(x)) << PCU_TRIM0_LVD50_TRIM_SHIFT)) & PCU_TRIM0_LVD50_TRIM_MASK)


/**
 * @}
 */ /* end of group PCU_Register_Masks */


/**
 * @}
 */ /* end of group PCU_Peripheral_Access_Layer */

#endif /* PSIP_PCU_H */

