/*==================================================================================================
*   Platform             : CORTEXM
*   Peripheral           : PCACHE
*   Dependencies         : none
*
*   Autosar Version      : 4.4.0
*   Autosar Revision     : ASR_REL_4_4_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : 0.8.0
*
*   (c) Copyright 2020-2026 Yuntu Microelectronics co.,ltd.
*   All Rights Reserved.
*
*   YUNTU Confidential. This software is owned or controlled by YUNTU and may only be
*   used strictly in accordance with the applicable license terms. By expressly
*   accepting such terms or by downloading, installing, activating and/or otherwise
*   using the software, you are agreeing that you have read, and that you agree to
*   comply with and are bound by, such license terms. If you do not agree to be
*   bound by the applicable license terms, then you may not retain, install,
*   activate or otherwise use the software.
==================================================================================================*/

#ifndef PCACHE_LLD_H_
#define PCACHE_LLD_H_

/**
*   @file
*
*   @internal
*   @addtogroup Pcache_Lld
*   @{
*/

#ifdef __cplusplus
extern "C"
{
#endif

/*==================================================================================================
*                                        INCLUDE FILES
==================================================================================================*/

#include "Platform_Types.h"

/*==================================================================================================
*                              SOURCE FILE VERSION INFORMATION
==================================================================================================*/
#define PCACHE_LLD_VENDOR_ID                      (180)
#define PCACHE_LLD_AR_RELEASE_MAJOR_VERSION       (4)
#define PCACHE_LLD_AR_RELEASE_MINOR_VERSION       (4)
#define PCACHE_LLD_AR_RELEASE_REVISION_VERSION    (0)
#define PCACHE_LLD_SW_MAJOR_VERSION               (0)
#define PCACHE_LLD_SW_MINOR_VERSION               (8)
#define PCACHE_LLD_SW_PATCH_VERSION               (0)

/*==================================================================================================
*                                     FILE VERSION CHECKS
==================================================================================================*/

/*==================================================================================================
*                                      FUNCTION PROTOTYPES
==================================================================================================*/



/**
 * @brief         Enables P-CACHE. Issues DSB/ISB barriers and sets the cache enable bit.
 * @autosar       N/A
 *
 * @details       Service ID: N/A
 *                Sync/Async: Synchronous
 *                Reentrancy: Non Reentrant
 *                Available via: Pcache_Lld.h
 *
 * @return No return value.
*/
void Pcache_Lld_EnableCache(void);

/**
 * @brief         Disables P-CACHE. Issues DSB/ISB barriers and clears the cache enable bit.
 * @autosar       N/A
 *
 * @details       Service ID: N/A
 *                Sync/Async: Synchronous
 *                Reentrancy: Non Reentrant
 *                Available via: Pcache_Lld.h
 *
 * @return No return value.
*/
void Pcache_Lld_DisableCache(void);

#if PLATFORM_PCACHE_VERSION == 1

/**
 * @brief         Enables flash cache mode by setting the corresponding control bit.
 * @autosar       N/A
 *
 * @details       Service ID: N/A
 *                Sync/Async: Synchronous
 *                Reentrancy: Non Reentrant
 *                Available via: Pcache_Lld.h
 *
 * @return No return value.
*/
void Pcache_Lld_EnableFlashCache(void);

/**
 * @brief         Disables flash cache mode by clearing the corresponding control bit.
 * @autosar       N/A
 *
 * @details       Service ID: N/A
 *                Sync/Async: Synchronous
 *                Reentrancy: Non Reentrant
 *                Available via: Pcache_Lld.h
 *
 * @return No return value.
*/
void Pcache_Lld_DisableFlashCache(void);

/**
 * @brief         Enables RAM cache mode by clearing the OCRAM cache disable bit.
 * @autosar       N/A
 *
 * @details       Service ID: N/A
 *                Sync/Async: Synchronous
 *                Reentrancy: Non Reentrant
 *                Available via: Pcache_Lld.h
 *
 * @return No return value.
*/
void Pcache_Lld_EnableRamCache(void);

/**
 * @brief         Disables RAM cache mode by setting the OCRAM cache disable bit.
 * @autosar       N/A
 *
 * @details       Service ID: N/A
 *                Sync/Async: Synchronous
 *                Reentrancy: Non Reentrant
 *                Available via: Pcache_Lld.h
 *
 * @return No return value.
*/
void Pcache_Lld_DisableRamCache(void);

#endif
/**
 * @brief         Invalidates all cache lines. Issues DSB/ISB barriers and triggers invalidate commands for all ways, waiting for completion.
 * @autosar       N/A
 *
 * @details       Service ID: N/A
 *                Sync/Async: Synchronous
 *                Reentrancy: Non Reentrant
 *                Available via: Pcache_Lld.h
 *
 * @return No return value.
*/
void Pcache_Lld_InvalidateAll(void);

/**
 * @brief         Configures P-CACHE according to input flags: sets flash and RAM cache modes, invalidates all cache lines, and enables or disables the cache based on the modes.
 * @autosar       N/A
 *
 * @details       Service ID: N/A
 *                Sync/Async: Synchronous
 *                Reentrancy: Non Reentrant
 *                Available via: Pcache_Lld.h
 *
 * @param[in] FlashCacheEnable: TRUE to enable flash cache, FALSE to disable.
 * @param[in] RamCacheEnable: TRUE to enable RAM cache, FALSE to disable.
 * @return No return value.
*/
void Pcache_Lld_Init(boolean FlashCacheEnable, boolean RamCacheEnable);


#ifdef __cplusplus
}
#endif

#endif /* PCACHE_LLD_H_ */

/** @} */

