/**
*   @file    pSIP_Eeprom.h
*   @version
*
*   @brief   AUTOSAR Eeprom register map
*   @details Register map for EEPROM
*
*   @addtogroup EEPROM_MODULE
*   @{
*/
/*==================================================================================================
*   Project              : YTMicro AUTOSAR 4.4.0 MCAL
*   Platform             : ARM
*   Peripheral           : Eeprom
*   Dependencies         : none
*
*   Autosar Version      : V4.4.0
*   Autosar Revision     : ASR_REL_4_4_REV_0000
*   Autosar Conf.Variant :
*   SW Version           : V0.8.0
*
*   (c) Copyright 2020-2026 Jiangsu Yuntu Microelectronics CO,. LTD.
*   All Rights Reserved.
==================================================================================================*/
/*==================================================================================================
==================================================================================================*/

#ifndef PSIP_EEPROM_H
#define PSIP_EEPROM_H

/*=================================================================================================
*                                        INCLUDE FILES
=================================================================================================*/

#include "Std_Types.h"

/*==================================================================================================
*                              EEPROM REGISTER MAP
==================================================================================================*/

/**
 * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer
 * @{
 */


/** EEPROM - Size of Registers Arrays */
#define EEPROM_ADDR_PROT_COUNT           (1)

/* EEPROM Register Layout Typedef */
typedef struct
{
    uint32 CTRL;                               /**< Control Register, offset: 0x0000 */
    uint32 STS;                                /**< Status Register, offset: 0x0004 */
    uint32 CMD;                                /**< Command Register, offset: 0x0008 */
    uint32 CMD_PROT;                           /**< Command Protect Register, offset: 0x000C */
    uint32 TIMING1;                            /**< Timing 1 Control Register, offset: 0x0010 */
    uint32 TIMING2;                            /**< Timing 2 Control Register, offset: 0x0014 */
    uint32 RESERVED6[ 2];                      /**< RESERVED6, offset: 0x0018 */
    uint32 ERR_INJECT_CTRL;                    /**< Error Inject Control, offset: 0x0020 */
    uint32 ADDR_PROT[ 1];                      /**< Address Protect Register, offset: 0x0024 */
    uint32 RESERVED9[ 2];                      /**< RESERVED9, offset: 0x0028 */
    uint32 ECCERR_ADDR;                        /**< ECC Error Address, offset: 0x0030 */
    uint32 ECCERR_CNT;                         /**< ECC Error Count, offset: 0x0034 */
    uint32 RESERVED12[114];                     /**< RESERVED12, offset: 0x0038 */
    uint32 CMD_UNLOCK;                         /**< EEPROM Command Unlock, offset: 0x0200 */
    uint32 RESERVED14[63];                     /**< RESERVED14, offset: 0x0204 */
    uint32 RESERVED15;                         /**< RESERVED15, offset: 0x0300 */
    uint32 RESERVED16;                         /**< RESERVED16, offset: 0x0304 */

} EEPROM_Type, *EEPROM_MemMapPtr;

/** Number of instances of the EEPROM module. */
#define EEPROM_INSTANCE_COUNT                        (1u)

/* EEPROM base address */
#define EEPROM_BASE_ADDR32                                (0x4003C000U)
#define EEPROM                                            ((volatile EEPROM_Type *)(EEPROM_BASE_ADDR32))

/** Array initializer of EEPROM peripheral base addresses */
#define EEPROM_BASE_ADDRS                                  { EEPROM_BASE_ADDR32 }
/** Array initializer of EEPROM peripheral base pointers */
#define EEPROM_BASE_PTRS                                   { EEPROM }

#define EEPROM_CTRL_OFFSET32                               (0x0000U)                    /**< Offset for Control Register */
#define EEPROM_STS_OFFSET32                                (0x0004U)                    /**< Offset for Status Register */
#define EEPROM_CMD_OFFSET32                                (0x0008U)                    /**< Offset for Command Register */
#define EEPROM_CMD_PROT_OFFSET32                           (0x000CU)                    /**< Offset for Command Protect Register */
#define EEPROM_TIMING1_OFFSET32                            (0x0010U)                    /**< Offset for Timing 1 Control Register */
#define EEPROM_TIMING2_OFFSET32                            (0x0014U)                    /**< Offset for Timing 2 Control Register */
#define EEPROM_ERR_INJECT_CTRL_OFFSET32                    (0x0020U)                    /**< Offset for Error Inject Control */
#define EEPROM_ADDR_PROT_OFFSET32(x)                       (0x0024U + ((x) * (4U)))     /**< Offset for Address Protect Register */
#define EEPROM_ECCERR_ADDR_OFFSET32                        (0x0030U)                    /**< Offset for ECC Error Address */
#define EEPROM_ECCERR_CNT_OFFSET32                         (0x0034U)                    /**< Offset for ECC Error Count */
#define EEPROM_CMD_UNLOCK_OFFSET32                         (0x0200U)                    /**< Offset for EEPROM Command Unlock */


/**
 * @addtogroup EEPROM Register Mask
 * @{
 */
/* EEPROM_CTRL Register */
#define EEPROM_CTRL_LPEN_MASK                                 (0x80000000U)
#define EEPROM_CTRL_LPEN_SHIFT                                (31U)
#define EEPROM_CTRL_LPEN(x)                                   (((uint32)(((uint32)(x)) << EEPROM_CTRL_LPEN_SHIFT)) & EEPROM_CTRL_LPEN_MASK)
#define EEPROM_CTRL_AUTO_FUNC_EN_MASK                         (0x1000000U)
#define EEPROM_CTRL_AUTO_FUNC_EN_SHIFT                        (24U)
#define EEPROM_CTRL_AUTO_FUNC_EN(x)                           (((uint32)(((uint32)(x)) << EEPROM_CTRL_AUTO_FUNC_EN_SHIFT)) & EEPROM_CTRL_AUTO_FUNC_EN_MASK)
#define EEPROM_CTRL_PRESCALER_MASK                            (0xFF0000U)
#define EEPROM_CTRL_PRESCALER_SHIFT                           (16U)
#define EEPROM_CTRL_PRESCALER(x)                              (((uint32)(((uint32)(x)) << EEPROM_CTRL_PRESCALER_SHIFT)) & EEPROM_CTRL_PRESCALER_MASK)
#define EEPROM_CTRL_WE_MASK                                   (0x1000U)
#define EEPROM_CTRL_WE_SHIFT                                  (12U)
#define EEPROM_CTRL_WE(x)                                     (((uint32)(((uint32)(x)) << EEPROM_CTRL_WE_SHIFT)) & EEPROM_CTRL_WE_MASK)
#define EEPROM_CTRL_RWS_MASK                                  (0xF00U)
#define EEPROM_CTRL_RWS_SHIFT                                 (8U)
#define EEPROM_CTRL_RWS(x)                                    (((uint32)(((uint32)(x)) << EEPROM_CTRL_RWS_SHIFT)) & EEPROM_CTRL_RWS_MASK)
#define EEPROM_CTRL_CMD_VERIFY_EN_MASK                        (0x80U)
#define EEPROM_CTRL_CMD_VERIFY_EN_SHIFT                       (7U)
#define EEPROM_CTRL_CMD_VERIFY_EN(x)                          (((uint32)(((uint32)(x)) << EEPROM_CTRL_CMD_VERIFY_EN_SHIFT)) & EEPROM_CTRL_CMD_VERIFY_EN_MASK)
#define EEPROM_CTRL_FAILIE_MASK                               (0x10U)
#define EEPROM_CTRL_FAILIE_SHIFT                              (4U)
#define EEPROM_CTRL_FAILIE(x)                                 (((uint32)(((uint32)(x)) << EEPROM_CTRL_FAILIE_SHIFT)) & EEPROM_CTRL_FAILIE_MASK)
#define EEPROM_CTRL_ACCERRIE_MASK                             (0x8U)
#define EEPROM_CTRL_ACCERRIE_SHIFT                            (3U)
#define EEPROM_CTRL_ACCERRIE(x)                               (((uint32)(((uint32)(x)) << EEPROM_CTRL_ACCERRIE_SHIFT)) & EEPROM_CTRL_ACCERRIE_MASK)
#define EEPROM_CTRL_UNRECOVERRIE_MASK                         (0x4U)
#define EEPROM_CTRL_UNRECOVERRIE_SHIFT                        (2U)
#define EEPROM_CTRL_UNRECOVERRIE(x)                           (((uint32)(((uint32)(x)) << EEPROM_CTRL_UNRECOVERRIE_SHIFT)) & EEPROM_CTRL_UNRECOVERRIE_MASK)
#define EEPROM_CTRL_RECOVERRIE_MASK                           (0x2U)
#define EEPROM_CTRL_RECOVERRIE_SHIFT                          (1U)
#define EEPROM_CTRL_RECOVERRIE(x)                             (((uint32)(((uint32)(x)) << EEPROM_CTRL_RECOVERRIE_SHIFT)) & EEPROM_CTRL_RECOVERRIE_MASK)
#define EEPROM_CTRL_DONEIE_MASK                               (0x1U)
#define EEPROM_CTRL_DONEIE_SHIFT                              (0U)
#define EEPROM_CTRL_DONEIE(x)                                 (((uint32)(((uint32)(x)) << EEPROM_CTRL_DONEIE_SHIFT)) & EEPROM_CTRL_DONEIE_MASK)
/* EEPROM_STS Register */
#define EEPROM_STS_IDLE_MASK                                  (0x80U)
#define EEPROM_STS_IDLE_SHIFT                                 (7U)
#define EEPROM_STS_IDLE(x)                                    (((uint32)(((uint32)(x)) << EEPROM_STS_IDLE_SHIFT)) & EEPROM_STS_IDLE_MASK)
#define EEPROM_STS_CMD_FAIL_MASK                              (0x10U)
#define EEPROM_STS_CMD_FAIL_SHIFT                             (4U)
#define EEPROM_STS_CMD_FAIL(x)                                (((uint32)(((uint32)(x)) << EEPROM_STS_CMD_FAIL_SHIFT)) & EEPROM_STS_CMD_FAIL_MASK)
#define EEPROM_STS_ACCERR_MASK                                (0x8U)
#define EEPROM_STS_ACCERR_SHIFT                               (3U)
#define EEPROM_STS_ACCERR(x)                                  (((uint32)(((uint32)(x)) << EEPROM_STS_ACCERR_SHIFT)) & EEPROM_STS_ACCERR_MASK)
#define EEPROM_STS_UNRECOVERR_MASK                            (0x4U)
#define EEPROM_STS_UNRECOVERR_SHIFT                           (2U)
#define EEPROM_STS_UNRECOVERR(x)                              (((uint32)(((uint32)(x)) << EEPROM_STS_UNRECOVERR_SHIFT)) & EEPROM_STS_UNRECOVERR_MASK)
#define EEPROM_STS_RECOVERR_MASK                              (0x2U)
#define EEPROM_STS_RECOVERR_SHIFT                             (1U)
#define EEPROM_STS_RECOVERR(x)                                (((uint32)(((uint32)(x)) << EEPROM_STS_RECOVERR_SHIFT)) & EEPROM_STS_RECOVERR_MASK)
#define EEPROM_STS_DONE_MASK                                  (0x1U)
#define EEPROM_STS_DONE_SHIFT                                 (0U)
#define EEPROM_STS_DONE(x)                                    (((uint32)(((uint32)(x)) << EEPROM_STS_DONE_SHIFT)) & EEPROM_STS_DONE_MASK)
/* EEPROM_CMD Register */
#define EEPROM_CMD_CMD_MASK                                   (0xFFU)
#define EEPROM_CMD_CMD_SHIFT                                  (0U)
#define EEPROM_CMD_CMD(x)                                     (((uint32)(((uint32)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK)
/* EEPROM_CMD_PROT Register */
#define EEPROM_CMD_PROT_CMD_PROT_MASK                         (0x7FFU)
#define EEPROM_CMD_PROT_CMD_PROT_SHIFT                        (0U)
#define EEPROM_CMD_PROT_CMD_PROT(x)                           (((uint32)(((uint32)(x)) << EEPROM_CMD_PROT_CMD_PROT_SHIFT)) & EEPROM_CMD_PROT_CMD_PROT_MASK)
/* EEPROM_TIMING1 Register */
#define EEPROM_TIMING1_TPGS_MASK                              (0xFF0000U)
#define EEPROM_TIMING1_TPGS_SHIFT                             (16U)
#define EEPROM_TIMING1_TPGS(x)                                (((uint32)(((uint32)(x)) << EEPROM_TIMING1_TPGS_SHIFT)) & EEPROM_TIMING1_TPGS_MASK)
#define EEPROM_TIMING1_TPROG_MASK                             (0xFFU)
#define EEPROM_TIMING1_TPROG_SHIFT                            (0U)
#define EEPROM_TIMING1_TPROG(x)                               (((uint32)(((uint32)(x)) << EEPROM_TIMING1_TPROG_SHIFT)) & EEPROM_TIMING1_TPROG_MASK)
/* EEPROM_TIMING2 Register */
#define EEPROM_TIMING2_TERASE_MASK                            (0xFFFFFFU)
#define EEPROM_TIMING2_TERASE_SHIFT                           (0U)
#define EEPROM_TIMING2_TERASE(x)                              (((uint32)(((uint32)(x)) << EEPROM_TIMING2_TERASE_SHIFT)) & EEPROM_TIMING2_TERASE_MASK)
/* EEPROM_ERR_INJECT_CTRL Register */
#define EEPROM_ERR_INJECT_CTRL_ECCERR_INJ_EN_MASK             (0xE0000000U)
#define EEPROM_ERR_INJECT_CTRL_ECCERR_INJ_EN_SHIFT            (29U)
#define EEPROM_ERR_INJECT_CTRL_ECCERR_INJ_EN(x)               (((uint32)(((uint32)(x)) << EEPROM_ERR_INJECT_CTRL_ECCERR_INJ_EN_SHIFT)) & EEPROM_ERR_INJECT_CTRL_ECCERR_INJ_EN_MASK)
#define EEPROM_ERR_INJECT_CTRL_ECCERR_INJ_ADDR_MASK           (0x1FFFU)
#define EEPROM_ERR_INJECT_CTRL_ECCERR_INJ_ADDR_SHIFT          (0U)
#define EEPROM_ERR_INJECT_CTRL_ECCERR_INJ_ADDR(x)             (((uint32)(((uint32)(x)) << EEPROM_ERR_INJECT_CTRL_ECCERR_INJ_ADDR_SHIFT)) & EEPROM_ERR_INJECT_CTRL_ECCERR_INJ_ADDR_MASK)
/* EEPROM_ADDR_PROT Register */
#define EEPROM_ADDR_PROT_FLASH_ADDR_PROT_MASK                 (0xFFFFFFFFU)
#define EEPROM_ADDR_PROT_FLASH_ADDR_PROT_SHIFT                (0U)
#define EEPROM_ADDR_PROT_FLASH_ADDR_PROT(x)                   (((uint32)(((uint32)(x)) << EEPROM_ADDR_PROT_FLASH_ADDR_PROT_SHIFT)) & EEPROM_ADDR_PROT_FLASH_ADDR_PROT_MASK)
/* EEPROM_ECCERR_ADDR Register */
#define EEPROM_ECCERR_ADDR_ERR_FLASH_ADDR_MASK                (0xFFFFFFFFU)
#define EEPROM_ECCERR_ADDR_ERR_FLASH_ADDR_SHIFT               (0U)
#define EEPROM_ECCERR_ADDR_ERR_FLASH_ADDR(x)                  (((uint32)(((uint32)(x)) << EEPROM_ECCERR_ADDR_ERR_FLASH_ADDR_SHIFT)) & EEPROM_ECCERR_ADDR_ERR_FLASH_ADDR_MASK)
/* EEPROM_ECCERR_CNT Register */
#define EEPROM_ECCERR_CNT_ECCERR_CNT_MASK                     (0x7FFU)
#define EEPROM_ECCERR_CNT_ECCERR_CNT_SHIFT                    (0U)
#define EEPROM_ECCERR_CNT_ECCERR_CNT(x)                       (((uint32)(((uint32)(x)) << EEPROM_ECCERR_CNT_ECCERR_CNT_SHIFT)) & EEPROM_ECCERR_CNT_ECCERR_CNT_MASK)
/* EEPROM_CMD_UNLOCK Register */
#define EEPROM_CMD_UNLOCK_CMD_UNLOCK_KEY_MASK                 (0xFFFFFFFFU)
#define EEPROM_CMD_UNLOCK_CMD_UNLOCK_KEY_SHIFT                (0U)
#define EEPROM_CMD_UNLOCK_CMD_UNLOCK_KEY(x)                   (((uint32)(((uint32)(x)) << EEPROM_CMD_UNLOCK_CMD_UNLOCK_KEY_SHIFT)) & EEPROM_CMD_UNLOCK_CMD_UNLOCK_KEY_MASK)


/**
 * @}
 */ /* end of group EEPROM_Register_Masks */


/**
 * @}
 */ /* end of group EEPROM_Peripheral_Access_Layer */

#endif /* PSIP_EEPROM_H */

